1. Field of the Invention
The present invention relates to a printed wiring board and manufacturing method therefor, and particularly relates to a wiring method in a multilayer printed wiring board.
2. Description of the Related Art
As for a conventional high-density packaging structure of a printed wiring (circuit) board, a module or a packaging structure is known which uses a printed wiring board in a multilayer structure having a conductor layer and an insulation layer alternately stacked thereon, and has an active component such as a semiconductor IC chip (bear chip or die) or a passive component such as a resistor and a capacitor embedded therein. Such a multilayer structure generally has connection holes such as a via hole and a contact hole formed in between interlayers, and these connection holes are used to electrically connect a conductor layer with an electrode of the embedded electronic component provided in different layers.
For instance, Japanese Patent Laid-Open No. 2003-179351 describes a wiring method for connecting an upper conductor layer with a lower conductor layer, in a multilayer substrate including an insulation layer, an upper conductor layer and a lower conductor layer, the upper and lower layers respectively provided on the upper part and the lower part of the insulation layer, by the steps of: forming an aperture having the same shape and size as those of a spot of an irradiating laser beam on the upper conductor layer; irradiating the insulation layer with the laser beam by using an aperture pattern of the upper conductor layer as a mask (conformal mask); piercing a via so as to expose the lower conductor layer to be a wiring body from the insulation layer; and forming a conformal plated layer in the inner part of the via and on the upper conductor layer. Japanese Patent Laid-Open No. 2003-179351 also describes a copper direct method for forming a via through both the insulation layer and a copper foil as a method of using no mask. Japanese Patent Laid-Open No. 2001-239386 describes a general method of forming a via in a printed wiring board by irradiating a copper-clad laminate made up of a base material affixed with a copper foil with a carbon dioxide laser to form a hole toward the base material from above the copper foil.
In the above described conventional wiring method involving via forming, however, because of a steep angle defined by the surface of the lower conductor layer (land) formed in the bottom of the opened via and the inner wall surface of the via, it would be difficult to sufficiently secure the thickness of the plated film in the periphery of the opening of the via (angle in the upper part of the via) when the inner part of the via is plated, which causes a plating failure in the portion, and as a result, may cause a lowered reliability in the connection between the bottom wall (land) of the via to be a wiring body and the upper conductor layer.
As a result of various investigations, the present inventors confirmed that a plated film has less adhesion in the periphery of the opening in the upper part of the via than other parts, and that the plated film tends to become locally and excessively thin in the portion, for instance, in a method of forming a pattern of a conductor layer with an aperture having a size equal to or smaller than a diameter of an irradiating laser beam on the insulation layer, and irradiating the insulation layer with a laser having a beam diameter equal to or larger than the aperture through the conformal mask to form a via, as in a conformal mask method described in Japanese Patent Laid-Open No. 2003-179351, and also in a method of forming an aperture having a larger size than the beam diameter of the laser in the conductor layer and irradiating the conductor layer with the laser beam to form a via.
In recent years, in particular, a terminal pitch and a wiring pitch of components in a printed circuit board have rapidly been narrowed (fine pitched) so as to respond to the demand for higher packaging density, and as a result, the via has progressively been made to have a higher aspect ratio. In addition, it is an urgent task to thin the plated film itself, so that the lowered connection reliability due to a plating failure in the via will be more serious problem in the future. A module and a package having an electronic component such as a semiconductor IC chip mounted thereon particularly have a great number of the vias, so that it is an extremely important challenge to secure the connection reliability for 100% of vias, in order to secure and keep the product reliability.
The copper direct method of forming a via penetrating both the insulation layer and the copper foil as disclosed in Japanese Patent Laid-Open No. 2003-179351 and the method of forming the via by irradiating the conductor layer with a laser to penetrate both the insulation layer and the conductor layer without forming a mask by patterning the upper conductor layer as disclosed in Japanese Patent Laid-Open No. 2001-239386 are not much different in that it is difficult to sufficiently secure the thickness of a plated film in the periphery of the opening of the via when plating the via afterward. Moreover, Japanese Patent Laid-Open No. 2001-239386 describes that the method calls for removal of a burr in a copper foil formed in the periphery of the pierced via, with a wet etching technique, so that in this regard, the method has a problem in securing the connection reliability.
Thus, the present invention has been made in view of such circumstances, and is directed to providing a printed wiring board in which a plating failure can be prevented in a connection hole such as a via to be formed in the printed wiring board, thereby can enhance the connection reliability and can sufficiently cope with the trend of finer pitches, and providing a manufacturing method therefor.